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IDT54/74FCT388915T 70/100/133/150 3.3V LOW SKEW PLL-BASED CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Integrated Device Technology, Inc.
3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)
IDT54/74FCT388915T 70/100/133/150 PRELIMINARY
is fed back to the PLL at the FEEDBACK input resulting in essentially zero delay across the device. The PLL consists of * 0.5 MICRON CMOS Technology the phase/frequency detector, charge pump, loop filter and * Input frequency range: 10MHz - f2Q Max. spec VCO. The VCO is designed for a 2Q operating frequency (FREQ_SEL = HIGH) range of 40MHz to f2Q Max. * Max. output frequency: 150MHz The IDT54/74FCT388915T provides 8 outputs with 350ps * Pin and function compatible with FCT88915T, MC88915T skew. The Q5 output is inverted from the Q outputs. The 2Q * 5 non-inverting outputs, one inverting output, one 2x runs at twice the Q frequency and Q/2 runs at half the Q output, one /2 output; all outputs are TTL-compatible frequency. * 3-State outputs The FREQ_SEL control provides an additional / 2 option in * Output skew < 350ps (max.) the output path. PLL _EN allows bypassing of the PLL, which * Duty cycle distortion < 500ps (max.) is useful in static test modes. When PLL_EN is low, SYNC * Part-to-part skew: 1ns (from tPD max. spec) input may be used as a test clock. In this test mode, the input * 32/-16mA drive at CMOS output voltage levels frequency is not limited to the specified range and the polarity * VCC = 3.3V 0.3V of outputs is complementary to that in normal operation * Inputs can be driven by 3.3V or 5V components (PLL_EN = 1). The LOCK output attains logic HIGH when the * Available in 28 pin PLCC, LCC and SSOP packages PLL is in steady-state phase and frequency lock. When OE/ DESCRIPTION: RST is low, all the outputs are put in high impedance state and The IDT54/74FCT388915T uses phase-lock loop technol- registers at Q, Q and Q/2 outputs are reset. ogy to lock the frequency and phase of outputs to the input The IDT54/74FCT388915T requires one external loop filter reference clock. It provides low skew clock distribution for component as recommended in Figure 3. high performance PCs and workstations. One of the outputs
FEATURES:
FUNCTIONAL BLOCK DIAGRAM
FEEDBACK Phase/Freq. Detector Voltage Controlled Oscilator LF REF_SEL PLL_EN 0 1 Mux 2Q (/1) (/2) 1M u x 0
D Q
LOCK 0M u 1x Charge Pump
SYNC (0) SYNC (1)
Q0 Q1
Divide -By-2 FREQ_SEL OE/RST
CP R Q D CP R D CP R D CP D CP D CP D CP
R 3052 drw 01 R R R
Q
Q
Q2
Q
Q3
Q
Q4 Q5
Q
Q
Q/2
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(c)1995 Integrated Device Technology, Inc.
AUGUST 1995
DSC-4243/1
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IDT54/74FCT388915T 70/100/133/150 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
OE/RST GND VCC VCC Q5 Q4 2Q
4 FEEDBK REF_SEL SYNC(0) VCC(AN) LF GND(AN) SYNC(1) 5 6 7 8 9 10 11 12
3
2
1
28
27
26 25 24 23 Q/2 GND Q3 VCC Q2 GND LOCK
GND Q5 VCC OE/RST FEEDBACK REF_SEL SYNC(0) VCC(AN) LF GND(AN) SYNC(1) FREQ_SEL GND Q0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 SO28-7
28 27 26 25 24 23 22 21 20 19 18 17 16 15
Q4 VCC 2Q Q/2 GND Q3 VCC Q2 GND LOCK PLL_EN GND Q1 VCC
J28-1, L28-1
22 21 20 19
13
14
15
16
17
18
Q1
GND
GND
FREQ_SEL
PLL_EN
VCC
Q0
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SSOP TOP VIEW
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PLCC/LCC TOP VIEW
PIN DESCRIPTION
Pin Name SYNC(0) SYNC(1) REF_SEL FREQ_SEL FEEDBACK LF Q0-Q4 I/O I I I I I I O O O O O I I Reference clock input. Reference clock input. Chooses reference between SYNC (0) & SYNC (1). (Refer to functional block diagram). Selects between / 1 and / 2 frequency options. (Refer to functional block diagram). Feedback input to phase detector. Input for external loop filter connection. Clock output. Inverted clock output. Clock output (2 x Q frequency). Clock output (Q frequency / 2). Indicates phase lock has been achieved (HIGH when locked). Asynchronous reset (active LOW) and output enable (active HIGH). When HIGH, outputs are enabled. When LOW, outputs are in HIGH impedance. Disables phase-lock for low frequency testing. (Refer to functional block diagram).
3052 tbl 01
Description
Q5
2Q Q/2 LOCK OE/RST PLL_EN
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IDT54/74FCT388915T 70/100/133/150 3.3V LOW SKEW PLL-BASED CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Rating VTERM(2) Terminal Voltage with Respect to GND VTERM(3) Terminal Voltage with Respect to GND VTERM(4) Terminal Voltage with Respect to GND TA Operating Temperature TBIAS Temperature Under Bias TSTG Storage Temperature IOUT DC Output Current Commercial Military -0.5 to +4.6 -0.5 to +4.6 Unit V
CAPACITANCE (TA = +25C, f = 1.0MHz)
Symbol Parameter(1) CIN Input Capacitance COUT Output Capacitance Conditions VIN = 0V VOUT = 0V Typ. 4.5 5.5 Max. Unit 6.0 pF 8.0
pF
3052 lnk 03
-0.5 to +7.0
-0.5 to +7.0
V
NOTE: 1. This parameter is measured at characterization but not tested.
-0.5 to VCC +0.5 0 to +70 -55 to +125 -55 to +125 -60 to +60
-0.5 to VCC +0.5 -55 to +125 -65 to +135 -65 to +150 -60 to +60
V C C C mA
3052 tbl 02 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Vcc terminals. 3. Input terminals. 4. Output and I/O terminals.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Commercial: TA = 0C to 70C, VCC = 3.3V 0.3V
Symbol VIH VIL II H II L IOZH IOZL VIK IODH IODL VOH VOL VH ICCL ICCH ICCZ Parameter Input HIGH Level Input LOW Level Input HIGH Current Input LOW Current High Impedance Output Current (3-State Output Pins) Clamp Diode Voltage Output Drive Current Output Drive Current Output HIGH Voltage Output LOW Voltage Input Hysteresis Quiescent Power Supply Current VCC = Max. Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max. VI = 5.5V VI = GND VO = VCC VO = GND VCC = Min., IIN = -18mA VCC = Max., VIN = VIH or VIL, VO = VCC = Min. VCC = Min. -- VCC = Max., VIN = GND or VCC (Test mode) 1.5V(3) VCC = Max., VIN = VIH or VIL, VO = 1.5V(3) IOH = -16mA IOL = 32mA Min. 2.0 -0.5 -- -- -- -- -- -36 50 2.4 (5) -- -- -- Typ.(2) -- -- -- -- -- -- -0.7 -- -- 3.0 0.3 100 2.0 Max. 5.5 0.8 1 1 1 1 -1.2 -- -- -- 0.5 -- 4.0 Unit V V A A A A V mA mA V V mV mA
NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, +25C ambient. 3. Not more than one output should be tested at one time. Duration of the test should not exceed one second. 4. This parameter is guaranteed but not tested. 5. VOH = VCC - 0.6V at rated current.
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IDT54/74FCT388915T 70/100/133/150 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol ICC ICCD CPD IC Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current(4) Power Dissipation Capacitance Total Power Supply Current (6) VCC = Max. VIN = VCC -2.1V(3) VIN = VCC VIN = GND -- -- -- 0.2 15 30 0.3 25 60 mA/ MHz pF mA VCC = Max. All Outputs Open 50% Duty Cycle VCC = Max. PLL_EN = 1, LOCK = 1, FEEDBACK = Q4 SYNC frequency = 50MHz. All bits loaded with 15pF VCC = Max. PLL_EN = 1, LOCK = 1, FEEDBACK = Q4 SYNC frequency = 50MHz. All bits loaded with 50 Thevenin termination and 20pF
3052 tbl 05 NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, +25C ambient. 3. Per TTL driven input. All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. It is derived with Q frequency as the reference. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (f) + ILOAD ICC = Quiescent Current (ICCL, ICCH and ICCZ) ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) f =2Q Frequency ILOAD = Dynamic Current due to load.
Test Conditions(1) VIN = VCC -0.6V(3)
Min. --
Typ.(2) 2.0
Max. 30
Unit A
--
90
120
mA
SYNC INPUT TIMING REQUIREMENTS
Symbol Parameter TRISE/FALL Rise/Fall Times, SYNC inputs (0.8V to 2.0V) Frequency Input Frequency, SYNC Inputs Duty Cycle Input Duty Cycle, SYNC Inputs Min. -- Max. 3.0 Unit ns
10.0 (1) 25%
2Q fmax 75%
MHz --
3052 tbl 06
OUTPUT FREQUENCY SPECIFICATIONS
Max. Symbol f2Q fQ fQ/2 Parameter Operating frequency 2Q Output Operating frequency Q0-Q4, Q5 Outputs Operating frequency Q/2 Output Min. 40 20 10 70 70 35 17.5 100 100 50 25
(2)
133 133 66.7 33.3
150 150 75 37.5
Unit MHz MHz MHz
3052 tbl 07 NOTES: 1. Note 7 in "General AC Specification Notes" and Figure 3 describes this specification and its actual limits depending on the feedback connection. 2. Maximum operating frequency is guaranteed with the part in a phase locked condition and all outputs loaded.
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IDT54/74FCT388915T 70/100/133/150 3.3V LOW SKEW PLL-BASED CLOCK DRIVER
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SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Symbol tRISE/FALL All Outputs tPULSE WIDTH (3) Q, Q, Q/2 outputs (3) tPULSE WIDTH 2Q Output (3) Parameter Rise/Fall Time (between 0.8V and 2.0V) Output Pulse Width Q0-Q4, Q5, Q/2, @ 1.5V Output Pulse Width 2Q @ 1.5V Load = 50 to VCC/2, CL = 20pF 0.1F from LF to Analog GND (5) Load = 50 to VCC/2, CL = 20pF Condition(1) Load = 50 to VCC/2, CL = 20pF Min.* 0.2 (2) Max.* 1.5 0.5tCYCLE + 0.5(5) 0.5tCYCLE + 0.7(5) +0.5 Unit ns ns ns ns
Load = 50 to 0.5tCYCLE - 0.5(5) VCC/2, CL = 20pF 0.5tCYCLE - 0.7(5) -0.5
SYNC input to FEEDBACK delay tPD (3) (measured at SYNC0 or 1 and FEEDBACK SYNC-FEEDBACK input pins) tSKEWr (rising)(3,4) tSKEWf (falling)(3,4) tSKEWall tLOCK (6)
(3,4)
Output to Output Skew between outputs 2Q, Q0-Q4, Q/2 (rising edges only) Output to Output Skew between outputs Q0-Q4 (falling edges only) Output to Output Skew 2Q, Q/2, Q0-Q4 rising, Q5 falling Time required to acquire Phase-Lock from time SYNC input signal is received Output Enable Time OE/RST (LOW-to-HIGH) to Q, 2Q, Q/2, Q Output Disable Time OE/RST (HIGH-to-LOW) to Q, 2Q, Q/2, Q
--
250
ps
-- -- 1(2)
250 350 10
ps ps ms
tPZH tPZL tPHZ tPLZ
3(2) 3(2)
14 14
ns ns
3052 tbl 08 GENERAL AC SPECIFICATION NOTES: * PRELIMINARY. 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested. 3. These specifications are guaranteed but not production tested. 4. Under equally loaded conditions, as specified under test conditions and at a fixed temperature and voltage. 5. tCYCLE = 1/frequency at which each output (Q, Q, Q/2 or 2Q) is expected to run. 6. With VCC fully powered-on and an output properly connected to the FEEDBACK pin. tLOCK Max. is with C1 = 0.1F, tLOCK Min. is with C1 = 0.01F. (Where C1 is loop filter capacitor shown in Figure 2).
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IDT54/74FCT388915T 70/100/133/150 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
NOTES: 7. The wiring diagrams and written explanations of Figure 3 demonstrate the input and output frequency relationships for various possible feedback configurations. The allowable SYNC input range to stay in the phase-locked condition is also indicated. There are two allowable SYNC frequency ranges, depending on whether FREQ_SEL is HIGH or LOW. Also it is possible to feed back the Q5 output, thus creating a 180 phase shift between the SYNC input and the Q outputs. The table below summarizes the allowable SYNC frequency range for each possible configuration.
FREQ_SEL Level HIGH HIGH HIGH HIGH LOW LOW LOW LOW
Feedback Output Q/2 Any Q (Q0-Q4)
Allowable SYNC Input Frequency Range (MHZ) 10 to (2x _Q fMAX Spec)/4 20 to (2x_Q fMAX Spec)/2 20 to (2x_Q fMAX Spec)/2 40 to (2x_Q fMAX Spec) 5 to (2x_Q fMAX Spec)/8 10 to (2x_Q fMAX Spec)/4 10 to (2x_Q fMAX Spec)/4 20 to (2x_Q fMAX Spec)/2
Corresponding 2Q Output Frequency Range 40 to (2Q fMAX Spec) 40 to (2Q fMAX Spec) 40 to (2Q fMAX Spec) 40 to (2Q fMAX Spec) 20 to (2Q fMAX Spec)/2 20 to (2Q fMAX Spec)/2 20 to (2Q fMAX Spec)/2 20 to (2Q fMAX Spec)/2
Phase Relationship of the Q Outputs to Rising SYNC Edge 0 0 180 0 0 0 180 0
3052 tbl 09
Q5
2X_Q Q/2 Any Q (Q0-Q4)
Q5
2X_Q
8. The tPD spec describes how the phase offset between the SYNC input and the output connected to the FEEDBACK input, varies with process, temperature and voltage. Measurements were made with a 10MHz SYNC input and Q/2 output as feedback. The phase measurements were made at 1.5V. The Q/ 2 output was terminated at the FEEDBACK input with 100 to VCC and 100 to ground. tPD measurements were made with the loop filter connection shown below:
External Loop Filter
LF
0.1F
C1
Analog GND
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IDT54/74FCT388915T 70/100/133/150 3.3V LOW SKEW PLL-BASED CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
BOARD VCC
ANALOG VCC Analog loop filter section of the FCT388915T
10F Low Freq. Bypass
0.1F High Freq. Bypass
LF 0.1F (Loop Filter Cap)
ANALOG GND
BOARD GND
A separate Analog power supply is not necessary and should not be used. Following these prescribed guidelines is all that is necessary to use the FCT388915 in a normal digital environment.
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Figure 2. Recommended Loop Filter and Analog Isolation Scheme for the FCT388915T NOTES: 1. Figure 2 shows a loop filter and analog isolation scheme which will be effective in most applications. The following guidelines should be followed to ensure stable and jitter-free operation: All loop filter and analog isolation components should be tied as close to the package as possible. Stray current passing through the parasitics of long traces can cause undesirable voltage transients at the LF pin. b. The 10F low frequency bypass capacitor and the 0.1F high frequency bypass capacitor form a wide bandwidth filter that will minimize the 388915T's sensitivity to voltage transients from the system digital VCC supply and ground planes. If good bypass techniques are used on a board design near components which may cause digital VCC and ground noise, VCC step deviations should not occur at the 388915T's digital VCC supply. The purpose of the bypass filtering scheme shown in figure 2 is to give the 388915T additional protection from the power supply and ground plane transients that can occur in a high frequency, high speed digital system. c. The loop filter capacitor (0.1F) can be a ceramic chip capacitor, the same as a standard bypass capacitor. 2. In addition to the bypass capacitors used in the analog filter of figure 2 there should be a 0.1F bypass capacitor between each of the other (digital) four VCC pins and the board ground plane. This will reduce output switching noise caused by the 388915T outputs, in addition to reducing potential for noise in the "analog" section of the chip. These bypass capacitors should also be tied as close to the 388915T package as possible. a.
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IDT54/74FCT388915T 70/100/133/150 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
The frequency relationship shown here is applicable to all Q outputs (Q0, Q1, Q2, Q3 and Q4). 1:2 INPUT TO "Q" OUTPUT FREQUENCY RELATIONSHIP In this application, the Q/2 output is connected to the FEEDBACK input. The internal PLL will line up the positive edges of Q/2 and SYNC, thus the Q/2 frequency will equal the SYNC frequency. The Q outputs (Q0-Q4, Q5) will always run at 2X the Q/2 frequency, and the 2Q output will run at 4X the Q/2 frequency.
50 MHz signal 12.5 MHz feedback signal HIGH OE/RST Q5 FEEDBACK LOW 12.5 MHz input REF_SEL SYNC(0) VCC(AN) LF GND(AN) FQ_SEL Q0 HIGH Q1 PLL_EN HIGH
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25 MHz feedback signal HIGH OE/RST Q5 FEEDBACK LOW 25 MHz input REF_SEL SYNC(0) VCC(AN) LF GND(AN) FQ_SEL Q0 Q1 FCT388915T Q4
50 MHz signal
2Q Q/2 12.5 MHz signal 25 MHz "Q" Clock Outputs
Q3
Q2
PLL_EN HIGH
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Q4
2Q Q/2
HIGH
Q3 FCT388915T Q2
25 MHz "Q" Clock Outputs
Allowable Input Frequency Range: 20MHz to (f2Q MAX Spec)/2 (for FREQ_SEL HIGH) 10MHz to (f2Q MAX Spec)/4 (for FREQ_SEL LOW)
Figure 3b. Wiring Diagram and Frequency Relationships With Q4 Output Feedback
2:1 INPUT TO "Q" OUTPUT FREQUENCY RELATIONSHIP In this application, the 2Q output is connected to the FEEDBACK input. The internal PLL will line up the positive edges of 2Q and SYNC, thus the 2Q frequency will equal the SYNC frequency. The Q/2 output will always run at 1/4 the 2Q frequency, and the Q output will run at 1/2 the 2Q frequency.
50 MHz feedback signal HIGH OE/RST Q5 FEEDBACK Q4 2Q Q/2 12.5 MHz input 25 MHz "Q" Clock Outputs
Allowable Input Frequency Range: 10MHz to ( f2Q MAX Spec)/4 (for FREQ_SEL HIGH) 5MHz to (f2Q MAX Spec)/8 (for FREQ_SEL LOW)
Figure 3a. Wiring Diagram and Frequency Relationships With Q/2 Output Feedback
1:1 INPUT TO "Q" OUTPUT FREQUENCY RELATIONSHIP In this application, the Q4 output is connected to the FEEDBACK input. The internal PLL will line up the positive edges of Q4 and SYNC, thus the Q4 frequency (and the rest of the "Q" outputs) will equal the SYNC frequency. The Q/2 output will always run at 1/2 the Q frequency, and the 2Q output will run at 2X the Q frequency.
LOW 50 MHz input
REF_SEL SYNC(0) VCC(AN) LF GND(AN) FQ_SEL Q0 HIGH Q1 PLL_EN HIGH
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Q3 FCT388915T Q2
Allowable Input Frequency Range: 40MHz to (f2Q MAX Spec) (for FREQ_SEL HIGH) 20MHz to (f2Q MAX Spec)/2 (for FREQ_SEL LOW)
Figure 3c. Wiring Diagram and Frequency Relationships With 2Q Output Feedback
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IDT54/74FCT388915T 70/100/133/150 3.3V LOW SKEW PLL-BASED CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CMMU FCT388915T PLL 2f
CMMU
CPU CARD
CLOCK @f SYSTEM CLOCK SOURCE
CPU
CMMU
CMMU
CMMU
CMMU FCT388915T PLL 2f
CMMU
CPU CARD
CPU
CMMU
DISTRIBUTE CLOCK @f
CMMU
CMMU
CLOCK @2f at point of use
FCT388915T PLL 2f
MEMORY CONTROL
MEMORY CARDS CLOCK @2f at point of use
3052 drw 13
Figure 4. Multiprocessing Application Using the FCT388915T for Frequency Multiplication and Low Board-to-Board skew
FCT388915T System Level Testing Functionality When the PLL_EN pin is LOW, the PLL is bypassed and the FCT388915T is in low frequency "test mode". In test mode (with FREQ_SEL HIGH), the 2Q output is inverted from the selected SYNC input, and the Q outputs are divide-by-2 (negative edge triggered) of the SYNC input, and the Q/2 output is divide-by-4 (negative edge triggered). With FREQ_SEL LOW the 2Q output is divide-by-2 of the SYNC, the Q outputs divide-by-4, and the Q/2 output divide-by-8. These relationships can be seen in the block diagram. A recommended test configuration would be to use SYNC0 or SYNC1 as the test clock input, and tie PLL_EN and REF_SEL together and connect them to the test select logic. This functionality is needed since most board-level testers run at 1 MHz or below, and theFCT 388915T cannot lock onto that low of an input frequency. In the test mode described above, any test frequency test can be used.
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IDT54/74FCT388915T 70/100/133/150 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS 50 TO VCC/2, CL = 20PF
VCC VCC
VCC
ENABLE AND DISABLE TEST CIRCUIT
6.0V
100 VIN Pulse Generator RT D.U.T. 20pF 100 CL
RT
3052 drw 05
VOUT
VIN Pulse Generator D.U.T.
500 VOUT
GND
500
3052 drw 06
PROPAGATION DELAY, OUTPUT SKEW
SYNC INPUT (SYNC (1) or SYNC (0)) 1.5V tPD t CYCLE SYNC INPUT VCC/2
FEEDBACK INPUT
VCC/2 Q/2 OUTPUT t SKEWALL Q0-Q4 OUTPUTS tCYCLE "Q" OUTPUTS 1.5V Q5 OUTPUT VCC/2 2Q OUTPUT
3052 drw 08
t SKEWf
t SKEWr
t SKEWf
t SKEWr VCC/2
(These waveforms represent the configuration of Figure 3a) NOTES: 1. The FCT388915T aligns rising edges of the FEEDBACK input and SYNC input, therefore the SYNC input does not require a 50% duty cycle. 2. All skew specs are measured between the VCC/2 crossing point of the appropriate output edges. All skews are specified as "windows", not as deviation around a center point. 3. If a Q ouput is connected to the FEEDBACK input (this situation is not shown), the Q output frequency would match the SYNC input frequency, the 2Q output would run at twice the SYNC frequency and the Q/2 output would run at half the SYNC frequency.
ENABLE AND DISABLE TIMES
ENABLE CONTROL INPUT tPZL OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH SWITCH 6V tPZH SWITCH GND 1.5V 0V 3V 1.5V tPHZ 0.3V VOH 0V
3052 drw 07
SWITCH POSITION
3V 1.5V 0V 3V 0.3V VOL
DISABLE
tPLZ
Test Disable Low Enable Low Disable High Enable High
Switch 6V GND
3052 tbl 10 DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH 2. Pulse Generator for All Pulses: tF 2.5ns; tR 2.5ns
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IDT54/74FCT388915T 70/100/133/150 3.3V LOW SKEW PLL-BASED CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
XXXX IDT XX FCT Temp. Range Device Type X Speed X Package X Process Blank B J L PY 70 100 133 150 388915T 54 74 Commercial MIL-STD-883, Class B PLCC LCC SSOP 70MHz Max. Frequency 100MHz Max. Frequency 133MHz Max. Frequency 150MHz Max. Frequency 3.3V Low skew PLL-based CMOS clock driver -55C to +125C 0C to +70C
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